1. Field of the Invention
The present invention relates generally to high density integrated circuit devices, and more particularly to interconnect structures for multi-level three-dimensional stacked devices.
2. Description of Related Art
In the manufacturing of high density memory devices, the amount of data per unit area on an integrated circuit can be a critical factor. Thus, as the critical dimensions of the memory devices approach lithographic technology limits, techniques for stacking multiple levels of memory cells have been proposed in order to achieve greater storage density and lower costs per bit.
As the size of different components all multi-levels three-dimensional stacked devices is decreased, problems relating to breakdown voltage and current leakage arise due to the reduced thickness of various insulating layers. For example, the thickness of the electrical insulation surrounding plugs or other electrical conductors passing through different contact levels of an interconnect region can be increased in response to these concerns. However, doing so increases the resistance of the plugs by reducing their cross-sectional areas. Alternatively, the cross-sectional areas of the plugs can be maintained; this however tends to increase the spacing between the plugs and thereby reducing the device density. There is a similar concern creating to ground or other interlevel plugs which electrically contact some or all of the contact layers within the interconnect region. By minimizing the cross-sectional area of the interlevel plug, efficient spacing is achieved but at the expense of limiting the contact area between the interlevel plugs and the conductive layers of the various contact levels. Increasing the cross-sectional area of the interlevel plugs results in reduced the device density.